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CMOS Dual-Port RAM
SAE 81C80 A
CMOS IC Features
q q q q q q q q q q q q q q q
Processor interface with address and data bus plus signals ALE, WR, RD 8051-, 8096-compatible timing Memory capacity 504 bytes All functions fully static (excl. oscillator watchdog) Standby operation On-chip oscillator with separate clock output Eight scheduling registers Three loadable timers for processor monitoring or applicable as longterm timers Monitoring of internal oscillator (hardware watchdog) Three outputs for interrupt triggering (can be set on the bus) Fully asynchronous operation of two processors possible Data retention down to 1 V P-LCC-44 (SMD) package Extended temperature range from - 40 through 110 C CMOS technology Ordering Code Q67100-H8706
P-LCC-44-1
Type SAE 81C80 A
Package P-LCC-44-1 (SMD)
The SAE 81C80 A dual-port RAM (DPR) is a CMOS memory IC with a capacity of 504 bytes (figure 1). A very notable feature of this DPR is that it can be used by two microcontrollers (MCs) simultaneously and fully asynchronously. Each microcontroller uses the DPR like a normal static RAM. Thus, when comparing the circuit development of this DPR with that of standard memory, no extra effort is required. Access collisions are excluded, which is the pre-requisite for fast communication between the two MCs. The SAE 81C80 A DPR is ideally suited for multi-processor/multi-controller applications like master/slave configurations or controls where one controller aquires measured data and a second one controls the actuators (e.g. in motors, etc.). (See figures 2 and 3). Semiconductor Group 1 09.94
SAE 81C80 A
Pin Configuration (top view)
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SAE 81C80 A
Pin Definitions and Functions Pin No. 7 8 9 10 11 12 13 14 06 37 36 35 34 33 32 31 30 38 15 29 Symbol Function AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 A18 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 A28 ALE1 ALE2
Data and address bus port 1
Address 8 port 1
Data and address bus port 2
Address 8 port 1 Address latch enable port 1 Address latch enable port 2 These signals are for separating data and addresses on the bus. The address is stored on the falling edge of the signal. Read signal port 1 (active low) Read signal port 2 (active low) Write signal port 1 (active low) Write signal port 2 (active low) Chip select port 1 Chip select port 1 (active low) Chip select port 2 Chip select port 2 (active low) The chip-select inputs select a port when the two associated inputs are on active level.
5 39 4 40 3 2 41 42
RD1 RD2 WR1 WR2 CS1 CS1 CS2 CS2
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SAE 81C80 A
Pin No. 27
Symbol Function RES Reset input Resets the IC to a defined initial state when RES is low. At the same time the outputs WD1, WD2, WD3 are switched low for the duration of the reset pulse. The oscillator continues to operate. Power down Disables all other inputs and the oscillator when PD is low. Negative supply voltage Positive supply voltage Not connected Pin for crystal (must remain open for external clock supply). Pin for crystal or applying external clock Clock output Oscillator watchdog (open-drain output) High indicates that the oscillator is working. Open-drain outputs of three timers No function (must be connected) Open-drain outputs Outputs that can be controlled via the port for triggering an interrupt on a processor for example.
28 44 1 43 19 20 21 22 16 17 18 26 23 24 25
PD
VSS VDD
N.C. XTAL1 XTAL2 CLKQ WDO WD1 WD2 WD3
VSS
Int1 Int2 Int3
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4
SAE 81C80 A
Figure 1 Principle of the Dual-Port-RAM (DPR)
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SAE 81C80 A
Figure 2 Interfacing Master and Slave Processors by DPRs
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SAE 81C80 A
Figure 3 Dual-Port RAM used between Measured-Data Acquisition and the Actuators Functional Description Dual-Port RAM The SAE 81C80A is a 504-byte static RAM simultaneously accessible by two microcontrollers. The memory locations are selected via a multiplexed address/data bus and two chip-select inputs. The direction of data transfer is determined by the RD and WR inputs. There will be no undefined states when a memory location is concurrently accessed by two processors, even if they write simultaneously to the same memory location. Depending on the internal state of the access control and the actual physical sequence, the value one of the two ports will be stored. Also, if one memory location is read and written to at the same time, the data will not be mixed, i.e. either the original data or the new data are read out.
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7
SAE 81C80 A
Chip-Select Inputs The chip-select inputs affect signals WR and RD, but not the ALE input. Therefore, the ALE signal on the DPR (even if the DPR is not selected) must correspond to the specified values. To eliminate selection, it is sufficient if one of the two chip-select inputs becomes inactive when the falling edge of WR or RD appears. Reset The reset is necessary for setting the control units of the DPR to a defined initial state. It initializes the timer-mode registers with the values 0000XXX0B (timers 1 and 2) and 00000XX0B (timer 3). The INT outputs are set to 0. The reset input is a TTL input without Schmitt-trigger response. For this reason, neither an ALE nor a WR signal must be applied to the DPR if the voltage on the reset input is below VIH. The length of the Reset pulse must be greater than six clock (oscillator) cycles and the clock must be active. When the reset input is low the reset input is low, outputs WD1, WD2 and WD3 are set to low. After a reset these outputs are high. The scheduling registers are set to state 1 by reset. A reset is also necessary if the DPR is reactivated from power-down, while the contents of the RAM and oscillator remain unaffected. Power-Down Mode When the power-down mode (PD) is activated, all inputs (except PD and XTAL1, XTAL2) plus the oscillator are disabled. This means that any levels are possible on the remaining inputs. An active level on PD also produces an internal reset. Nevertheless, to ensure proper operation after deactivation of the power-down mode, an external reset should be made to bridge the time required by the oscillator for buildup. The outputs of the ports go highimpedance, while outputs CLKO, WDO, WD1, WD2, WD3, INT1, INT2 and INT3 are set to low. The PD input shows a Schmitt-trigger response. This allows VDD to be evaluated directly, for example (see application circuit).
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SAE 81C80 A
Interrupt Outputs The DPR has three interrupt outputs that can be set and reset directly by writing to an address (see table 1). The outputs are located in the same address range as the scheduling registers. However, only bits 2 and 3 are relevant for the interrupt outputs. At least one of bits 0 and 1 should be other than 1 to prevent the scheduling registers from being affected. The functions of the outputs are shown in the following table:
RES 1 1 1 1 0
Bit 3 0 0 1 1 -
Bit 2 0 1 0 1 -
Output no change 1 0 undefined 0
Oscillator Watchdog This part of the circuit is a fail-save mechanism for the oscillator. If the frequency of the clock is missing, the output switches to WDO low. The circuit works like an analog integrator. Below approx. 100 kHz, low pulses are produced on the output. The pulse width depends on the clock frequency. This part of the circuit should not be used at operating frequencies of les than 500 kHz. Supply Voltage To prevent any interference, the supply voltage of the DPR should be blocked as close as possible to the pins with a capacitor of approx. 100 nF (see application circuit).
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SAE 81C80 A
Timers The three timers are 24-bit counters with a clock frequency of fOSC/6. Each of the counters can be set by writing to three specific RAM addresses. The value is then simultaneously stored in the RAM and a buffer register of the timer. When the low byte is written, all three bytes are parallely stored in the reload register. The value in the reload register is kept in all operating modes until the associated low byte is written again. The counters are down-counters. They can be started by setting bit 7 in the associated timer-mode register (TMR). Each counter can be configured by a TMR. The bits of the TMRs have the following function: Bit 0: This bit provides overwrite protection for the reload register. Use: After writing to the reload registers and starting of the timer - by writing to the associated protection bit - the adjacent RAM area can be used without affecting the reload register (reset state = 0). Bit 4: It serves for switching the polarity of the output signal (reset state = 0). Bit 4 = 0; idle state 1, active 0 Bit 4 = 1; idle state 0, active 1 Bit 5: This bit switches the operating mode (reset state = 0). Bit 5 = 0 single-shot, i.e. when the counter is started, the output signal becomes active. After reaching zero, the output signal is reset. The timer has to be restarted to trigger another count cycle. The values from the reload register are then loaded into the counter. Bit 5 = 1 auto reload, i.e. when the counter is started, the value of the reload register is loaded into it. When zero is reached, the counter issues a pulse ( 4 s at 12 MHz), automatically reloads the original value and the entire operation starts again. In this way a frequency can be set with a resolution of 24 bits. Because of the pulse width of eight timer clock pulses, however, the shortest period is limited to nine timer clock pulses (tosx ! 6). If a new start pulse appears in the count cycle (even without "STOP"), no pulse is issued and the counter is reloaded. Bit 6: In the reload mode the timer can be halted by setting this bit and resetting bit 5. (In a new start the contents of the counter are lost and that of the reload registers remain unaffected). Setting this bit starts the counter.
Bit 7:
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SAE 81C80 A
Only for the registers of timers 1 and 2 Bit 1-3: These are used together with bit 0 for switching the watchdog mode ON and OFF. Only for the register of timer 3 Bit 1-2: Reserved (should always be 0 for correct operation). Bit 3: Switches all three timers to test mode, i.e. only the upper twelve bits are used to generate the output signal (reset state = 0).
Watchdog Mode For timers 1 and 2 a special mode was implemented which can be used to monitor the two processors. In this mode there is a control register (CR) for each timer (see table 1 for addresses). The watchdog mode is set by loading the TMR with the value 101X1111B, the polarity of the output signal being freely selectable with bit 4. This mode works similarly to the auto-reload mode, but neither the reload register nor the TMR can be altered. In the watchdog mode, the timer can only be restarted (and the output pulse suppressed) if the values 055H and 0AAH are successively written into the control register. The time between these two write operations is random, but the sequence must be completed before the timer has run down, i.e. the output pulse is generated. No value may be written into either the TMR or CR between the two write operations, otherwise the sequence has to be started again. To reset the timer to the normal mode, first the value 055H has to be written into the CR, then the value 010X0000B into the TMR, and finally the value 0AAH into the CR. Here, too, if any other value is written into either of the two registers during the sequence, the entire operation has to be started again. The time between the accesses is random. The timer operation in watchdog mode is illustrated in the appendix in an 8051 example program. Note: The relevant bits for changing the timer state to watchdog mode are bit 0 - bit 3; the shown pattern is the only one, which makes sense for this mode.
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SAE 81C80 A
Figure 4 Bit Assignment of Timer-Mode Registers for Timer 1 and 2 Bit 7
Software start (= 1)
Bit 6
Timer stop (= 1) for autoreload
Bit 5
Mode (autoreload = 1, singleshot = 0)
Bit 4
Polarity of output pulse (High = 0)
Bit 3
Only for watchdog mode (normal mode = 0)
Bit 2
Only for watchdog mode (normal mode = 0)
Bit 1
Only for watchdog mode (normal mode = 0)
Bit 0
Protection (= 1) against overwriting of reload register
Figure 5 Bit Assignment of Timer-Mode Registers for Timer 3 Bit 7
Software start (= 1)
Bit 6
Timer stop (= 1) for autoreload
Bit 5
Mode (autoreload = 1, singleshot = 0)
Bit 4
Polarity of output pulse (High = 0)
Bit 3
Test (= 1) switches timer to test mode
Bit 2
Bit 1
Bit 0
Reserved Reserved Protection (normal (normal (= 1) mode = 0) mode = 0) against overwriting of reload register
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SAE 81C80 A
Access Collisions With a RAM which can be written to or read simultaneously by two controllers, different kinds of access collision are possible: 1. Simultaneous read access to the same memory location from both ports; 2. One port reads the same memory location which the other port writes to concurrently; 3. Concurrent write access to the same memory location from both ports; 4. Read access to a logically linked data block by one port, while the other port modifies the same data block. The SAE 81C80A dual-port RAM avoids the first three types of access collision by hardware. The fourth problem can be solved by user software. The standard solution for the access collisions described above would be as follows: before accessing the memory area, an additional memory location must be established by setting an access flag (semaphore). This would necessitate three memory operations: - First access: read the flag and check whether the data area is free. - Second access: write the flag with the data for reservation. - Third access: read the flag and make sure that your own reservation has not been overwritten by the other port. Only after this sequence would a microcontroller be privileged for access and could write or read to the data area without the risk of contention. With the SAE 81C80A dual-port RAM this access routine is simplified using scheduling registers.
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SAE 81C80 A
Scheduling Registers Note: The assignment of a memory area to a scheduling register is defined by the user software of both controllers With the scheduling registers synchronization can be done with only one access because the reservation is performed during reading. The other port cannot overwrite it. This means that a scheduling register is written by reading, unless it was occupied. The description above shows that these registers are no ordinary RAM locations. They are formed by a finite state machine (FSM), which can assume the following four states (see figure 6): - - - - State 1: port 1 was the previous owner and the register is free. State 2: port 1 occupies the register. State 3: port 2 was the previous owner and the register is free. State 4: port 2 occupies the register.
The state of a register can be read out from the particular address, but causes also a change in the state of the FSM (arrows in figure 6). Reading produces 2-bit information: - Bit 0 is the owner bit. It is set when the reading port is or was the owner of a register. - Bit 1 is the occupied bit. It is set when a register has been reserved by a port. - Bit 2 through 7 are always 0. Reserving is done by reading a register and enabling by writing to it XXXXXX11B (pay attention to the interrupt outputs of bits 2 and 3!). Thus a correct protocol using the scheduling registers takes the following form: 1. Read the scheduling register. 2. Check whether the occupied bit is set and the owner bit is not set (i.e. the other port has reserved). If so, go back to 1, otherwise continue. 3. Process the data area. 4. Enable the scheduling register by writing 03H to the address of the register 5. End In cases where accessing of a data area requires prior reading of or writing to this data area by the second processor, a separate evaluation of the occupied bit and owner bit can be done in step 2: 2a. Owner bit self? If so, continue to 2c, otherwise to 2b. 2b. Occupied bit self? If so, continue to 2c, otherwise to 3. 2c. Enable the scheduling register by writing 03H to the address of the register (continue with 1).
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SAE 81C80 A
The following applies only to the scheduling registers: Usually, in the case of a concurrent access by both processors, writing has priority over reading. However, a simultaneous read or write access from the two ports means that port 1 has priority over port 2. The addresses of the scheduling registers are listed in table 1. The assignment of scheduling registers to specific data areas is made by the user. The software (of both controllers) should be configured so that, prior to accessing a logically related data area, the associated scheduling register is accessed first (according to the above sequence). So the assignment of the various dual-port RAM address spaces to scheduling registers will depend solely on the structure of the user software.
Figure 6 Diagram Showing the Various States of the Scheduling Registers Only the two least significant bits of the data are shown (in converted commas). Semiconductor Group 15
SAE 81C80 A
Notes: 1. The owner bit indicates the last owner of a register. 2. Only if the port is owner of the register will writing change the state. 3. The reset state is state 1. 4. The FSM is symmetrical. Therefore, the two processors can use the same program. Table 1 Address Assignment of DPR Registers Register Scheduling register 1 Scheduling register 2 Scheduling register 3 Scheduling register 4 Scheduling register 5 Scheduling register 6 Scheduling register 7 Scheduling register 8 Timer-mode register 1 Timer-mode register 2 Timer-mode register 3 High-byte timer 1 Medium-byte timer 1 Low-byte timer 1 Address 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 1E0H 1E4H 1E8H 1E3H 1E2H 1E1H Register High-byte timer 2 Medium-byte timer 2 Low-byte timer 2 High-byte timer 3 Medium-byte timer 3 Low-byte timer 3 Control-register timer 1 Control-register timer 2 Interrupt output 1 Interrupt output 1 Interrupt output 1 Address 1E7H 1E6H 1E5H 1EBH 1EAH 1E9H 1ECH 1EDH 1F8H 1F9H 1FAH
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SAE 81C80 A
Figure 7 Memory Map
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SAE 81C80 A
Block Diagram Semiconductor Group 18
SAE 81C80 A
Absolute Maximum Ratings
TA = - 40 to 110 C; all voltages referred to VSS
Parameter Symbol min. Storage temperature Total power dissipation Power dissipation per output Input voltage Supply voltage Limit Values typ. - - - - - max. 125 500 50 C mW mW Unit
Tstg Ptot PQ VI VDD
- 50 - - - 0.5 - 0.5
VDD + 0.5 V
6 V
Operating Range Supply voltage Supply current (w/o loading of outputs) Operating frequency Ambient temperature Standby current Data-retention voltage
VDD IDD fS TA IDD VDH
4.5 - - - 40 - 1
5 - - - - -
5.5 20 12 110 1 -
V mA MHz C A V
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SAE 81C80 A
DC Characteristics
TA = 25 C; all voltages referred to VSS
Parameter Symbol Limit Values min. All Input Signals Except XTAL2 and PD H-input voltage L-input voltage Input capacitance Input current max. Unit Test Condition
VIH VIL CI II
2.2 0 - -
VDD
0.8 10 1
V V pF A
- - - -
XTAL2 (as external clock input) H-input voltage L-input voltage Input capacitance
VIH VIL CI
3.5 0 -
VDD
0.5 10
V V pF
- - -
PD (Schmitt-trigger characteristics) H-input voltage L-input voltage Input capacitance
VIH VIL CI
VDD - 1
0 -
VDD
1.0 10
V V pF
- - -
Output Signals AD10-17, AD20-27 H-output voltage L-output voltage
VQH VQL
2.4 -
VDD
0.4
V V
IQ = 0.5 mA IQ = 1.6 mA
Output Signals WD1, WD2, WD3, WD0 (open drain, weak pull-up) L-output voltage Output Signal Clock-Out H-output voltage L-output voltage Load capacitance Semiconductor Group
VQL
-
0.4
V
IQ = 1.6 mA
VQH VQL CL
2.4 - - 20
- 0.4 80
V V pF
IQ = 0.5 mA IQ = 1.6 mA
-
SAE 81C80 A
AC Characteristics The AC characteristics apply throughout the operating range TA = 25 C. Parameter Symbol min. Read cycle time Write cycle time ALE pulse width Address setup to ALE low Address hold after ALE low RD pulse width WR pulse width ALE low to RD or WR active Data hold after RD high ALE low to valid data out RD low to data valid (only scheduling registers) Valid data in after WR low WR low to ALE high Data setup before WR high Data hold after WR high Delay RD low to both chip select active Limit Values max. - - - - - - - - 30 290 2 tOSC + 20 30 - - - 20 20 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tCYR tCYW tLHLL tAVLL tLLAX tRLRH tWLWH tLLWL tRHDX tLLDV tRLDV tDVWL tWLLH tQVWH tWHQX tRLCH
300 + tLHLL 440 + tLHLL 40 30 40 120 120 30 0 - - - 150 30 30 - - 0 0
Delay WR low to both chip select active tWLCH Set-up of chip select to RD *) Set-up of chip select to WR *)
*) For deselection
tCLRL tCLWL
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SAE 81C80 A
AC Characteristics (cont'd) The AC characteristics apply throughout the operating range TA = 25 C. Parameter Symbol min. Active pulse length of timer outputs Oscillator period High time Low time Limit Values max. 48 tOSC - - - ns ns ns ns Unit
tACT tOSC tOSCH tSCL
48 tOSC 83 35 35
Pulse Diagram 1 Semiconductor Group 22
SAE 81C80 A
Pulse Diagram 2 Note to Chip Select Timing: The shown timing is not necessary, if the device is always activated or deactivated. This means either of CS or CS or both may be constant "high" or "low".
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SAE 81C80 A
Pulse Diagram 3
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SAE 81C80 A
Example of Application Circuit 1)
1)
Design proposal (non-obligatory)
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SAE 81C80 A
Appendix 8051 Program for Timer Operation in Watchdog Mode HBYTE TMR CR REST1 REST2 WDOFF EQU EQU EQU EQU EQU EQU 1E3H 1E0H 1ECH 055H 0AAH 040H ; Address high byte reload register ; Address timer-mode register ; Address control register ; 1st value to restart timer ; 2nd value to restart timer ; Value to switch off watchdog mode
; Load reload register MOV CLR MOVX DEC MOV MOVX DEC MOVX DPTR, #HBYTE A @DPTR,A DPL A, #0FFH @DPTR,A DPL @DPTR,A
; Set watchdog mode and start timer MOV DEC MOVX ; Reset timer MOV MOV MOVX MOV MOVX DPTR, #KR A, #REST1 @DPTR,A A, #REST2 @DPTR,A A, #0AFH DPL @DPTR,A
; Switch off watchdog mode and halt timer
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SAE 81C80 A
8051 Program for Timer Operation in Watchdog Mode (cont'd) MOV MOV MOVX MOV MOV MOVX MOV MOV MOVX ; END DPTR, #KR A, #REST1 @DPTR,A A, #WDOFF DPTR, #TMR @DPTR,A A, #REST2 DPTR, #KR @DPTR,A
Semiconductor Group
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